Analog to digital converters with sufficient dynamic range and linearity become increasingly difficult to implement as the sampling rates increase. Improving the performance of wideband analog to digital converters is a long standing problem and a number of approaches have been developed to address this issue. One approach in the prior art is to use time interleaved analog to digital converters, which are exemplified by U.S. Pat. No. 5,294,926 to Corcoran, issued Mar. 15, 1994. In that approach the signal is fed to a bank of analog to digital converters and the sampling of the signal is time interleaved between the analog to digital converters (ADC) so that the first sample is taken by the first ADC, the second sample by the second ADC and so on until the last ADC takes a sample and then the sampling order repeats starting with the first ADC. The samples from the ADCs are then recombined. The sample rate of any one of the analog to digital converters is reduced; however, mismatches between the analog to digital converters can cause amplitude and phase errors.
Another approach is use a filter bank to filter the wideband input signal into a set of lower bandwidth input signals. The lower bandwidth input signals can then be converted to digital form with ADCs operating at lower sample rates and then the outputs from the ADCs are recombined. The filter bank approach for reducing ADC sample rates is exemplified by U.S. Pat. No. 5,568,142 to Velazquez et al. issued Oct. 22, 1996 and by U.S. Pat. No. 6,476,749 to Yeap et al. issued Nov. 5, 2002.
Such a system for analog to digital conversion 10 is shown in FIG. 1. The wideband input signal 12 is fed into filters 14, which subdivide the wideband input signal 12 into a set of lower bandwidth signals that are each then fed into sample and hold circuits 16 and then to analog to digital converters 18. The outputs of the analog to digital converters 18 are digitally recombined in digital recombiner 20 to form a digital output 22, which is the digital representation of input signal 12.
In the prior art the filters 14 have different center frequencies to cover the bandwidth of the wideband input signal; however, each filter 14 has the same operational bandwidth. This has the advantage that the hardware downstream of each filter 14 is identical including the sample and hold circuit 16 and the ADC 18. Because all of the operational bandwidths of the filters 14 are identical, each sample and hold circuit 16, as shown in FIG. 1, is clocked at the same rate.
A disadvantage of the prior art system is that capacitors in the sample and hold circuits 16 may see large signal swings and if, as a result, the sample and hold circuits 16 cannot react fast enough to the large signal swings the sample and hold circuit 16 will introduce errors that effectively limit the performance of the analog to digital conversion system. Because the performance of the sample and hold circuits 16 is a major limiter to the performance of the filter bank approach for wideband analog to digital conversion, any improvement to the performance of the sample and hold circuits 16 can help improve the signal to noise ratio and the signal to noise plus distortion ratio of the analog to digital conversion system.
What is needed is a system that improves the performance of the sample and hold circuits or limits large signal swings at the input of the sample and hold circuits. If the stress on the sample and hold circuits can be limited then the performance of the analog the digital conversion system can be improved. The embodiments of the present disclosure answer these and other needs.